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HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
Integrated Device Technology, Inc.
IDT7024S/L
FEATURES:
* True Dual-Ported memory cells which allow simultaneous access of the same memory location * High-speed access -- Military: 20/25/35/55/70ns (max.) -- Commercial: 15/17/20/25/35/55ns (max.) * Low-power operation -- IDT7024S Active: 750mW (typ.) Standby: 5mW (typ.) -- IDT7024L Active: 750mW (typ.) Standby: 1mW (typ.) * Separate upper-byte and lower-byte control for multiplexed bus compatibility * IDT7024 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading
more than one device * M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave * Busy and Interrupt Flags * On-chip port arbitration logic * Full on-chip hardware support of semaphore signaling between ports * Devices are capable of withstanding greater than 2001V electrostatic discharge. * Fully asynchronous operation from either port * Battery backup operation--2V data retention * TTL-compatible, single 5V (10%) power supply * Available in 84-pin PGA, 84-pin quad flatpack, 84-pin PLCC, and 100-pin Thin Quad Plastic Flatpack * Industrial temperature range (-40C to +85C) is available, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/WL
UBL
R/WR
UBR
LBL CEL OEL
LBR CER OER
I/O8L-I/O 15L I/O Control I/O0L-I/O 7L I/O Control
I/O8R-I/O 15R I/O0R-I/O 7R
BUSYL
(1,2)
BUSYR(1,2)
Address Decoder
12
A11L A0L
MEMORY ARRAY
12
Address Decoder
A11R A0R
NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull.
CEL OEL
R/WL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
CER OER
R/WR
SEML (2) INTL
M/S
SEMR INTR(2)
2740 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2740/6
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT7024 is a high-speed 4K x 16 Dual-Port Static RAM. The IDT7024 is designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by chip enable ( CE ) permits the on-chip circuitry of each port to enter
a very low standby power mode. Fabricated using IDT's CMOS high-performance technol ogy, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500W from a 2V battery. The IDT7024 is packaged in a ceramic 84-pin PGA, an 84pin quad flatpack, an 84-pin PLCC, and a 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
PIN CONFIGURATIONS (1,2)
I/O6L I/O5L I/O3L I/O7L I/O4L I/O2L I/O1L I/O0L GND
SEML
R/WL
A11L
VCC
CEL
UBL LBL
OEL
N/C
A10L
A9L
INDEX
I/O8L I/O9L I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R
11 10 9 8 7 6 5 4 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 IDT7024 J84-1 F84-2 84-PIN PLCC / FLATPACK TOP VIEW (3) 68 67 66 65 64 63 62 61 60 59 58 57 56 55
A8L
A7L A6L A5L A4L A3L A2L A1L A0L
INTL
BUSYL
GND M/S
BUSYR
INTR
I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L
VCC R/WL
SEML
I/O11R
I/O10R
I/O15R
CER
I/O12R
I/O14R GND
I/O13R
R/WR
I/O9R
N/C A11R
A10R
UBR LBR
OER
SEMR
GND
A9R
A8R
A7R
2740 drw 02
N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 69 7 68 8 67 9 66 10 IDT7024 65 11 PN100-1 64 12 63 13 100-PIN 62 14 TQFP (3) 61 15 TOP VIEW 60 16 59 17 58 18 57 19 56 20 55 21 54 22 53 23 52 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C A11L A10L A9L A8L A7L A6L
N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L
INTL
OEL
UBL LBL
CEL
54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
A0R A1R A2R A3R A4R A5R A6R
Index
BUSYL
GND M/S
INTR
BUSYR
A0R A1R A2R A3R A4R N/C N/C N/C N/C
NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of the actual part-marking.
I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R
R/WR GND
UBR LBR
6.15
SEMR
N/C A11R A10R A9R A8R A7R A6R A5R
OER
CER
2740 drw 03
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D) (1,2)
63 61 60 58 55 54 51 48 46 45 42
11
I/O7L
66
I/O5L
64
I/O4L
62
I/O2L
59
I/O0L
56
OEL
49
SEML
50
LBL
47
A11L
44
A10L
43
A7L
40
10
I/O10L
67
I/O8L
65
I/O6L
I/O3L
I/O1L
57
UBL
53
CEL
52
N/C
A9L
A8L
41
A5L
39
09
I/O11L
69
I/O9L
68
GND
VCC
R/WL
A6L
38
A4L
37
08
I/O13L
72
I/O12L
71 73 33
A3L
35
A2L
34
INTL
07
I/O15L
75
I/O14L
70
VCC
74
IDT7024 G84-3 84-PIN PGA TOP VIEW(3)
BUSYL
32
A0L
31
36
06
I/O0R
76
GND
77
GND
78
GND
28
M/S
29
INTR
A1L
30
05
I/O1R
79
I/O2R
80
VCC
A0R
BUSYR
27
26
04
I/O3R
81
I/O4R
83 7 11 12
A2R
23
A1R
25
03
I/O5R
82 1
I/O7R
2 5
GND
8
GND
10
SEMR
14 17 20
A5R
22
A3R
24
02
I/O6R
84 3
I/O9R
I/O10R
4
I/O13R
6
I/O15R
9
R/WR
15
UBR
13
A11R
16
A8R
18
A6R
19
A4R
21
01
I/O8R A
I/O11R B
I/O12R C
I/O14R D
OER
E
LBR
F
CER
G
N/C H
A10R J
A9R K
A7R L
2740 drw 04
Index
NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power Ground
2740 tbl 1
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
CEL
R/WL
CER
R/WR
Grade Military Commercial
Ambient Temperature -55C to +125C 0C to +70C
GND 0V 0V
VCC 5.0V 10% 5.0V 10%
2740 tbl 02
OEL
A0L - A11L I/O0L - I/O15L
OER
A0R - A11R I/O0R - I/O15R
SEML UBL LBL INTL BUSYL
M/S VCC
SEMR UBR LBR INTR BUSYR
GND
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I - NON-CONTENTION READ/WRITE CONTROL
Inputs(1) Outputs
CE
H X L L L L L L X
R/W W X X L L L H H H X
OE
X X X X X L L L H
UB
X H L H L L H L X
LB
X H H L L H L L X
SEM
H H H H H H H H X
I/O8-15 High-Z High-Z DATAIN High-Z DATAIN DATAOUT High-Z High-Z
I/O0-7 High-Z High-Z High-Z DATAIN DATAIN High-Z Both Bytes Deselected
Mode Deselected: Power-Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only
DATAOUT Read Lower Byte Only High-Z Outputs Disabled
2740 tbl 03
DATAOUT DATAOUT Read Both Bytes
NOTE: 1. A0L -- A11L are not equal to A0R -- A11R.
TRUTH TABLE II - SEMAPHORE READ/WRITE CONTROL(1)
Inputs Outputs
CE
H X H X L L
R/W W H H
OE
L L X X X X
UB
X H X H L X
LB
X H X H X L
SEM
L L L L L L
I/O8-15
I/O0-7
Mode
DATAOUT DATAOUT Read Semaphore Flag Data Out DATAOUT DATAOUT Read Semaphore Flag Data Out DATAIN DATAIN -- -- DATAIN DATAIN -- -- Write I/O0 into Semaphore Flag Write I/O0 into Semaphore Flag Not Allowed Not Allowed
u u
X X
2740 tbl 04 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0 - I/O15). These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Rating Commercial Military -0.5 to +7.0 Unit V Terminal Voltage -0.5 to +7.0 with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current 0 to +70 -55 to +125 -55 to +125 50
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0 -- --
Max. Unit 5.5 0 6.0(2) 0.8 V V V V
2740 tbl 06
TA TBIAS TSTG IOUT
-55 to +125 -65 to +135 -65 to +150 50
C C C mA
VIL
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V.
NOTES: 2740 tbl 05 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc +0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period over VTERM > Vcc + 0.5V.
(TA = +25C, F = 1.0MHZ) TQFP ONLY
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Condition(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
CAPACITANCE(1)
NOTES: 2740 tbl 07 1. This parameter are determined by device characterization, but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V 10%)
IDT7024S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current
(1)
IDT7024L Min. -- -- -- 2.4 Max. 5 5 0.4 -- Unit A A V V
2740 tbl 08
Test Conditions VCC = 5.5V, VIN = 0V to VCC
Min. -- -- -- 2.4
Max. 10 10 0.4 --
Output Leakage Current Output Low Voltage Output High Voltage
CE = VIH, VOUT = 0V to VCC
IOL = 4mA IOH = -4mA
NOTE: 1. At Vcc < 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V 10%)
Symbol Parameter Dynamic Operating ICC Current (Both Ports Active) Test Condition CE"A"=VIL, Outputs Open SEM = VIH f = fMAX(3) 7024X15 7024X17 7024X20 Com'l. Only Com'l. Only Version Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. MIL S -- -- -- -- 160 370 L -- -- -- -- 160 320 COM S L MIL S L 170 170 -- -- 20 20 -- -- 105 105 -- -- 1.0 0.2 -- -- 100 100 310 260 -- -- 60 50 -- -- 190 160 -- -- 15 5 -- -- 170 140 170 170 -- -- 20 20 -- -- 105 105 -- -- 1.0 0.2 -- -- 100 100 310 260 -- -- 60 50 -- -- 190 160 -- -- 15 5 -- -- 170 140 160 160 20 20 20 20 95 95 95 95 1.0 0.2 1.0 0.2 90 90 90 90 290 240 90 70 60 50 240 210 180 150 30 10 15 5 225 200 155 130 7024X25 Typ.(2)Max. Unit 155 340 mA 155 280 155 155 16 16 16 16 90 90 90 90 1.0 0.2 1.0 0.2 85 85 85 85 265 220 80 65 60 50 215 180 170 140 30 10 15 5 200 170 145 120 mA mA mA mA
ISB1
Standby Current (Both Ports -- TTL Level Inputs)
CER = CEL = VIH SEMR = SEML = VIH
f = fMAX(3)
COM S L MIL S L COM S L MIL S L
ISB2
Standby Current (One Port -- TTL Level Inputs)
CE"A"=VIL and CE"B"=VIL(5)
Active Port Outputs Open f = fMAX
(3)
SEMR = SEML = VIH
ISB3 Full Standby Current Both Ports CEL and (Both Ports -- All CER >VCC - 0.2V
COM S CMOS Level Inputs) VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) L SEMR = SEML> VCC - 0.2V ISB4 Full Standby Current (One Port -- All CMOS Level Inputs)
CE"A" < 0.2 and CE"B" > VCC - 0.2V (5) SEMR = SEML> VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX(3)
MIL
S L
COM S L
NOTES: 2740 tbl 09 1. "X" in part numbers indicates power rating (S or L). 2. VCC = 5V, TA = +25C, and are not production tested. ICC DC = 120mA (typ.) 3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/ tRC, and using "AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Cont.) (VCC = 5.0V 10%)
7024X35 Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) ISB1 Standby Current (Both Ports -- TTL Level Inputs) ISB2 Standby Current (One Port -- TTL Level Inputs) ISB3 Full Standby Current (Both Ports -- All CMOS Level Inputs) Test Condition Version MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. S L S L S L S L S L S L S L S L S L S L Typ.(2) 150 150 150 150 13 13 13 13 85 85 85 85 1.0 0.2 1.0 0.2 80 80 80 80 Max. 300 250 250 210 80 65 60 50 190 160 155 130 30 10 15 5 175 150 135 110 7024X55 Typ.(2) 150 150 150 150 13 13 13 13 85 85 85 85 1.0 0.2 1.0 0.2 80 80 80 80 7024X70 Mil. Only Max. Typ.(2) Max. Unit 300 250 250 210 80 65 60 50 190 160 155 130 30 10 15 5 175 150 135 110 140 140 -- -- 10 10 -- -- 80 80 -- -- 1.0 0.2 -- -- 75 75 -- -- 300 250 -- -- 80 65 -- -- 190 160 -- -- 30 10 -- -- 175 150 -- -- mA mA mA mA mA
CE = VIL, Outputs Open SEM = VIH
f = fMAX(3)
CEL = CER = VIH SEMR = SEML = VIH
f = fMAX(3)
CE"A"=VIL and CE"B"=VIH(5)
Active Port Outputs Open f = fMAX(3)
SEMR = SEML = VIH Both Ports CEL and CER > VCC - 0.2V
ISB4
Full Standby Current (One Port -- All CMOS Level Inputs)
CE"A" < 0.2 and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX(3)
COM'L. VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V MIL.
COM'L.
NOTES: 2740 tbl 10 1. "X" in part numbers indicates power rating (S or L). 2. VCC = 5V, TA = +25C, and are not production tested. ICCDC = 120mA (typ.) 3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycleof 1/tRC, and using "AC Test Conditions"of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(VLC = 0.2V, VHC = VCC - 0.2V)(4)
Symbol VDR ICCDR tCDR(3) tR(3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition VCC = 2V Min. 2.0 MIL. COM'L. -- -- 0 tRC(2) Typ.(1) -- 100 100 -- -- Max. -- 4000 1500 -- -- ns ns
2740 tbl 11
Unit V A
CE > VHC
VIN > VHC or < VLC
SEM > VHC
NOTES: 1. TA = +25C, VCC = 2V, and are by characterization but are not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by device characterization but are not production tested. 4. At Vcc < 2.0V, input leakages are not defined.
DATA RETENTION WAVEFORM
DATA RETENTION MODE VCC 4.5V tCDR VDR 2V VDR 4.5V tR VIH
2740 drw 05
CE
VIH
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns Max. 1.5V 1.5V Figures 1 and 2
2740 tbl 12
5V 1250 DATAOUT
5V 1250 DATAOUT
BUSY INT
775
30pF
775
5pF
2740 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW) Including scope and Jig
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time
(3) (3)
Parameter
IDT7024X15 Com'l. Only Min. Max. 15 -- -- -- -- 3 3 -- -- 15 15 15 10 -- -- 10 -- 15 -- 15
IDT7024X17 Com'l. Only Min. Max. 17 -- -- -- -- 3 3 -- 0 -- 10 -- -- 17 17 17 10 -- -- 10 -- 17 -- 17
IDT7024X20 Min. 20 -- -- -- -- 3 3 -- 0 -- 10 -- Max. -- 20 20 20 12 -- -- 12 -- 20 -- 20
IDT7024X25 Min. 25 -- -- -- -- 3 3 -- 0 -- 10 -- Max. -- 25 25 25 13 -- -- 15 -- 25 -- 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns
Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1, 2)
Output High-Z Time(1, 2) Chip Enable to Power Up Time
(1,2) (1,2)
0 -- 10 --
Chip Disable to Power Down Time Semaphore Address Access
(3)
Semaphore Flag Update Pulse (OE or SEM)
IDT7024X35 Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time
(3)
IDT7024X55 Min. 55 -- -- -- -- 3 3 -- 0 -- 15 -- Max. -- 55 55 55 30 -- -- 25 -- 50 -- 55
Parameter
Min. 35 -- -- -- -- 3 3 --
Max. -- 35 35 35 20 -- -- 15 -- 35 -- 35
IDT7024X70 Mil. Only Min. Max. 70 -- -- -- -- 3 3 -- 0 -- 15 -- -- 70 70 70 35 -- -- 30 -- 50 -- 70
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2740 tbl 13
Byte Enable Access Time(3) Output Enable Access Time Output Hold from Address Change Output Low-Z Time(1, 2) Output High-Z Time(1, 2) Chip Enable to Power Up Time
(1,2) (1,2)
0 -- 15 --
Chip Disable to Power Down Time Semaphore Address Access(3)
Semaphore Flag Update Pulse (OE or SEM)
NOTES: 1. Transition is measured 500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM =VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM =VIL. 4. "X" in part numbers indicates power rating (S or L). 6.15
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
ADDR tAA (4) tACE tAOE
(4) (4)
tRC
CE
OE
tABE
UB, LB
(4)
R/W tLZ (1) DATAOUT VALID DATA
(4)
tOH
tHZ (2)
BUSYOUT
tBDD (3, 4)
2740 drw 07
NOTES: 1. Timing depends on which signal is asserted last, CE, OE, LB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB. 3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD. 5. SEM = VIH.
TIMING OF POWER-UP POWER-DOWN
CE
ICC ISB
tPU
50%
tPD
50%
2740 drw 08
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write Address Set-up Time(3) Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time(4) Write Enable to Output in High-Z(1, 2) Output Active from End-of-Write
(1, 2, 4) (1, 2) (3)
Parameter
IDT7024X15 Com'l. Only Min. Max. 15 12 12 0 12 0 10 -- 0 -- 0 5 5 -- -- -- -- -- -- -- 10 -- 10 -- -- --
IDT7024X17 Com'l. Only Min. Max. 17 12 12 0 12 0 10 -- 0 -- 0 5 5 -- -- -- -- -- -- -- 10 -- 10 -- -- --
IDT7024X20 Min. 20 15 15 0 15 0 15 -- 0 -- 0 5 5 Max. -- -- -- -- -- -- -- 12 -- 12 -- -- --
IDT7024X25 Min. 25 20 20 0 20 0 15 -- 0 -- 0 5 5 Max. -- -- -- -- -- -- -- 15 -- 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Address Valid to End-of-Write
SEM Flag Write to Read Time SEM Flag Contention Window
IDT7024X35 Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write(3) Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time(1, 2) Data Hold Time
(4) (1, 2) (3)
IDT7024X55 Min. 55 45 45 0 40 0 30 -- 0 -- 0 5 5 Max. -- -- -- -- -- -- -- 25 -- 25 -- -- --
Parameter
Min. 35 30 30 0 25 0 15 -- 0 -- 0 5 5
Max. -- -- -- -- -- -- -- 15 -- 15 -- -- --
IDT7024X70 Mil. Only Min. Max. 70 50 50 0 50 0 40 -- 0 -- 0 5 5 -- -- -- -- -- -- -- 30 -- 30 -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time SEM Flag Contention Window
NOTES: 2740 tbl 14 1. Transition is measured 500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. "X" in part numbers indicates power rating (S or L).
6.15
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8) W
tWC ADDRESS tHZ
(7)
OE
tAW
CE
or SEM
(9)
UB
or LB
(9)
tAS (6) R/W tWZ (7) DATAOUT
(4)
tWP(2)
tWR
(3)
tOW
(4)
tDW DATAIN
tDH
2740 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE UB LB CONTROLLED TIMING(1,5) CE, UB,
tWC ADDRESS tAW
CE or SEM
(9)
tAS
(6)
tEW (2)
tWR(3)
UB or LB (9)
R/W tDW DATAIN
2740 drw 10
tDH
NOTES: 1. R/W or CE or UB & LB must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a Low UB or LB and a Low CE and a Low R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end-of-write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W, UB, or LB. 7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured +/- 500mV steady state with the Output Test Load (Figure 2). 8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP for (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be met for either condition.
6.15
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tSAA A0-A2 VALID ADDRESS tWR tAW tEW tDW DATAIN VALID tAS R/W tSWRD tAOE tWP tDH VALID ADDRESS tACE tSOP DATAOUT VALID(2) tOH
SEM
I/O0
OE
Write Cycle Read Cycle
2740 drw 11
NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A" MATCH
SIDE
(2)
"A"
R/W"A"
SEM"A"
tSPS A0"B"-A2"B" MATCH
SIDE
(2)
"B"
R/W"B"
SEM"B"
2740 drw 12
NOTES: 1. D0R = D0L = VIL, CER = CEL = VIH, or both UB & LB = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 3. This parameter is measured from R/WA or SEMA going High to R/WB or SEMB going High. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the Semaphore flag.
6.15
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (6)
Symbol tBAA tBDA tBAC tBDC tAPS tBDD tWH tWB tWH tWDD tDDD Parameter Access Time from Address Match Disable Time from Address Not Matched Access Time from Chip Enable Low Disable Time from Chip Enable High
(2)
IDT7024X15 Com'l Only Min. Max. -- -- -- -- 5 -- 12 0 15 15 15 15 -- 18 -- -- -- 30 25
IDT7024X17 Com'l Only Min. Max. -- -- -- -- 5 -- 13 0 13 -- -- 17 17 17 17 -- 18 -- -- -- 30 25
IDT7024X20 Min. -- -- -- -- 5 -- 15 0 15 -- -- Max. 20 20 20 17 -- 30 -- -- -- 45 35
IDT7024X25 Min. -- -- -- -- 5 -- 17 0 17 -- -- Max. 20 20 20 17 -- 30 -- -- -- 50 35 Unit ns ns ns ns ns ns ns ns ns ns ns
S BUSY TIMING (M/S = VIH) BUSY BUSY BUSY BUSY
Arbitration Priority Set-up Time
BUSY
Disable to Valid Data(3)
Write Hold After BUSY(5)
BUSY
BUSY TIMING (M/S = VIL) S Input to Write(4)
(5)
Write Hold After BUSY
12 --
(1)
PORT-TO-PORT DELAY TIMING Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay --
IDT7024X35 Symbol BUSY TIMING (M/S = VIH) S tBAA tBDA tBAC tBDC tAPS tBDD tWH
BUSY BUSY BUSY BUSY
IDT7024X55 Min. -- -- -- -- 5 -- 25 Max. 45 40 40 35 -- 40 --
Parameter Access Time from Address Match Disable Time from Address Not Matched Access Time from Chip Enable Low Disable Time from Chip Enable High Disable to Valid Data(3)
(5)
Min. -- -- -- -- 5 -- 25
Max. 20 20 20 20 -- 35 --
IDT7024X70 Mil. Only Min. Max. -- -- -- -- 5 -- 25 45 40 40 35 -- 45 --
Unit ns ns ns ns ns ns ns
Arbitration Priority Set-up Time(2)
BUSY
Write Hold After BUSY Input to Write(4)
BUSY TIMING (M/S = VIL) S tWB tWH tWDD tDDD
BUSY
0 25 -- --
-- -- 60 45
0 25 -- --
-- -- 80 65
0 25 -- --
-- -- 95 80
ns ns ns ns
Write Hold After BUSY(5) Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay(1)
PORT-TO-PORT DELAY TIMING
NOTES: 2740 tbl 15 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write With Port-To-Port Delay (M/S = VIL)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0ns, tWDD - tWP (actual), or tDDD - tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention with port "A". 5. To ensure that a write cycle is completed on port "B" after contention with port "A". 6. "X" in part numbers indicates power rating (S or L).
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (M/S = VIH)(2,4,5) S
tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS (1) ADDR"B" tBAA MATCH tBDA tBDD VALID tDH
BUSY"B"
tWDD DATAOUT "B" tDDD
(3)
2740 drw 13
VALID
NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH (1)
R/W"B"
(2) 2740 drw 14
NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. Busy is asserted on port "B" Blocking R/W"B", until BUSY"B" goes High. 3. tWB is only for the Slave Version.
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1) S
ADDR"A" and "B" ADDRESSES MATCH
CE"A"
tAPS(2)
CE"B"
tBAC tBDC
2740 drw 14
BUSY"B"
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING (M/S = VIH)(1) S
ADDR"A" tAPS ADDR"B"
(2)
ADDRESS "N"
MATCHING ADDRESS "N" tBAA tBDA
2740 drw 16
BUSY"B"
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A". 2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 -- -- -- -- 15 15 0 0 -- -- -- -- 15 15 0 0 -- -- -- -- 20 20 0 0 -- -- -- -- 20 20 ns ns ns ns Parameter IDT7024X15 Com'l. Only Min. Max. IDT7024X17 Com'l. Only Min. Max. IDT7024X20 Min. Max. IDT7024X25 Min. Max. Unit
IDT7024X35 Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 -- -- -- -- 25 25 Parameter Min. Max.
IDT7024X55 Min. 0 0 -- -- Max. -- -- 40 40
IDT7024X70 Mil. Only Min. Max. 0 0 -- -- -- -- 50 50
Unit ns ns ns ns
2740 tbl 16
NOTE: 1. "X" in part numbers indicates power rating (S or L).
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
tWC ADDR"A" tAS
(3) (2)
INTERRUPT SET ADDRESS
tWR(4)
CE"A"
R/W"A" tINS(3)
INT"B"
2740 drw 17
tRC ADDR"B" tAS
(3)
INTERRUPT CLEAR ADDRESS (2)
CE"B"
OE"B"
tINR(3)
INT"B"
2740 drw 18
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A". 2. See Interrupt truth table. 3. Timing depends on which enable signal ( CE or R/W ) is asserted last. 4. Timing depends on which enable signal ( CE or R/W ) is de-asserted first.
TRUTH TABLES TRUTH TABLE III -- INTERRUPT FLAG(1,4)
Left Port R/WL W L X X X
CEL CE OEL OE
Right Port A11L-A0L FFF X X FFE
INTL INT
R/WR W X X L X
CER CE
OER OE
A11R-A0R X FFF FFE X
INTR INT
Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
2740 tbl 17
L X X L
X X X L
X X L(3) H
(2)
X L L X
X L X X
L
(2) (3)
H
X X
NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. INTR and INTL must be initialized at power-up.
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE IV -- ADDRESS BUSY ARBITRATION
Inputs Outputs
CE CEL
X H X L
CE CER
X X H L
A0L-A11L A0R-A11R
NO MATCH MATCH MATCH MATCH
BUSY (1) BUSY (1) BUSYL BUSYR
H H H (2) H H H (2)
Function Normal Normal Normal Write Inhibit(3)
NOTES: 2740 tbl 16 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7024 are push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE V -- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D15 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D15 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free Status
NOTES: 2740 tbl 19 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024. 2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
The IDT7024 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7024 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE High). When a port is enabled, access to the entire memory array is permitted.
memory location FFF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location FFF. The message (16 bits) at FFE or FFF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations FFE and FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all
INTERRUPTS
If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location FFE (HEX), where a write is defined as the CE = R/W = VIL per the Truth Table. The left port clears the interrupt by access address location FFE access when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to
6.15
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MASTER Dual Port RAM
CE
BUSYR
BUSYL
SLAVE Dual Port RAM
CE
BUSYR
BUSYL
MASTER Dual Port RAM
CE
BUSYR
BUSYL
BUSYL
SLAVE Dual Port RAM
CE
BUSYR BUSYR
2740 drw 19
BUSYL
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7024 RAMs.
applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. The busy outputs on the IDT 7024 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the busy indication for the resulting array requires the use of an external AND gate.
can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
SEMAPHORES
The IDT7024 is an extremely fast Dual-Port 4K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table where CE and SEM are both high. Systems which can best use the IDT7024 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7024's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the
WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS
When expanding an IDT7024 RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT7024 RAM the busy pin is an output if the part is used as a master (M/S pin = H), and the busy pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The busy arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse
6.15
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7024 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called "Token Passing Allocation." In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore's status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7024 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 - A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table III). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side's output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table III). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. This condition will continue until a one is written to the same semaphore request latch. Should the other side's semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side's request latch. The second side's flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a
6.15
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.
USING SEMAPHORES--SOME EXAMPLES
Perhaps the simplest application of semaphores is their application as resource markers for the IDT7024's Dual-Port RAM. Say the 4K x 16 RAM was to be divided into two 2K x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 2K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 2K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 2K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 2K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was "off-limits" to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory "WAIT" state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE SEMAPHORE READ
Figure 4. IDT7024 Semaphore Logic
R PORT SEMAPHORE REQUEST FLIP FLOP
Q D
D
Q
D0 WRITE
SEMAPHORE READ
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IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank B PF G J F 15 17 20 25 35 55 70 S L 7024 Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B 100-pin TQFP (PN100-1) 84-pin PGA (G84-3) 84-pin PLCC (J84-1) 84-pin Flatpack (F84-2) Commercial Only Commercial Only Speed in nanoseconds Military Only Standard Power Low Power 64K (4K x 16) Dual-Port RAM
2740 drw 21
6.15
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